This invention relates generally to automatic test equipment, and more specifically to a test instrument architecture for testing analog and mixed-signal electronic circuit assemblies.
Electronic circuit assemblies are typically tested at least once during their manufacture. One type of test is commonly known as functional testing, which is typically used to determine whether a unit under test (UUT) is capable of performing properly in its final operating environment. To this end, functional testing includes applying test stimuli to the UUT, observing responses generated by the UUT, and then determining whether the observed responses are acceptable for a properly functioning UUT.
Functional testing of circuit assemblies that include just analog or both analog and digital (i.e., mixed-signal) circuitry poses particular problems because the applied test stimuli and observed responses for these assemblies normally include many different waveforms and levels. Further, the observed responses must usually be evaluated relative to the test stimuli and sometimes each other. It is therefore often very challenging to generate the test stimuli and evaluate the responses in a way that closely simulates the final operating environments of these circuit assemblies.
Further, because functional testing of circuit assemblies typically occurs in a manufacturing environment, it is important that circuit assemblies are tested quickly and that problems in the assemblies are quickly identified, thereby keeping manufacturing costs down.
FIG. 1 shows conventional test equipment architecture 100 that may be used to perform functional testing of electronic circuit assemblies with analog and/or mixed-signal circuitry. Architecture 100 includes a number of discrete instruments 104, 106, and 108, which apply test stimuli to a UUT 112 and observe responses generated by the UUT 112.
Because the UUT 112 may include analog or mixed-signal circuitry, the instruments 104, 106, and 108 may include both analog and digital instruments. For example, the analog instruments may include a function generator for generating arbitrary waveforms or standard waveforms such as sine waves, triangle waves, or square waves; a multi-meter for measuring levels generated by the UUT 112; a waveform digitizer for sampling waveforms generated by the UUT 112 and storing the samples in memory (not shown) for subsequent analysis; or a timer/counter for making frequency, period, and time interval measurements.
In addition, the digital instruments may include devices for driving digital signals and sensing logic states on the UUT 112, and for measuring certain parameters of digital signals produced by the UUT 112. For example, one of the digital instruments may be used to measure logic levels of a digital signal at particular points in time.
The instruments 104, 106, and 108 are controlled by a host computer 102, which communicates with the instruments 104, 106, and 108 via a buss 114. The instruments 104, 106, and 108 are also normally connected to a buss 116, which carries triggering signals between the instruments. In a typical test configuration, the busses 114 and 116 are compatible with a standard interface such as HP-IB (IEEE-488) or VXIbus (IEEE-1155). Accordingly, the host computer 102 can be programmed to synchronize and control the operation of the instruments 104, 106, and 108 by specifying control and triggering signals carried by the busses 114 and 116, respectively.
As mentioned above, functional testing includes applying test stimuli to a UUT and observing responses generated by the UUT. For this reason, typical architecture 100 also includes a switch matrix 110, which is also controlled by the host computer 102 via the buss 114. The switch matrix 110 typically includes relays that are controlled to connect the instruments 104, 106, and 108 to selected nodes of the UUT 112. Nodes selected during functional testing are typically those nodes that are used in the final operating environment of the UUT.
For example, one or more of the instruments 104, 106, and 108 may be connected to nodes of the UUT 112 for applying test signals to the nodes. Further, response signals at other nodes of the UUT 112 may be measured by one or more of the instruments 104, 106, and 108. Accordingly, the host computer 102 may be programmed to actuate the relays in the switch matrix 110, thereby making necessary connections between the instruments 104, 106, and 108 and the nodes of the UUT 112 during a test session.
An example of architecture 100, in which both analog and digital instruments are connected to a UUT via a switch matrix, is illustrated in U.S. Pat. No. 4,070,565 assigned to TERADYNE(copyright), Inc., Walnut Creek, Calif., USA. Another example of test equipment architecture, in which driver instruments are connected directly to a UUT while measurement instruments are connected to the UUT through a switch matrix, is illustrated in U.S. Pat. No. 4,216,539, which is also assigned to TERADYNE(copyright), Inc.
Although test equipment architecture 100 has been used to perform functional testing of electronic circuit assemblies, we have recognized several shortcomings. For example, it was mentioned above that functional testing is typically used to determine whether a UUT can perform properly in its final operating environment. This generally means that architecture 100 must simulate the operating environment of the UUT as closely as possible and accurately evaluate the performance of the UUT in this simulated environment. However, conventional architecture 100 is based upon a collection of discrete instruments 104, 106, and 108, which frequently cannot simulate the operating environment as desired.
For example, if multiple measurements were needed to evaluate a signal at a node of a UUT, then the host computer 102 might control the switch matrix 110 to connect multiple measurement instruments to that node. However, this might subject the node to an unwanted loading condition that would generally not occur during normal operation.
Even if connecting multiple measurement instruments to a node did not result in an unwanted loading condition, the accuracy of the measurements may still be affected. In particular, different measurement instruments may have different input configurations, each with its own inherent delay characteristics. These delays may be unknown and variable and may even add up across conventional architecture 100, thereby further decreasing the accuracy of measurements.
Instead of connecting multiple measurement instruments to a single node, the host computer 102 may alternatively control the switch matrix 110 to connect the measurement instruments to a node in a sequential manner. Although this approach would probably avoid an unwanted loading condition, it would generally require that multiple measurements at a node be made at different times. This would preclude simultaneous measurements at the node and make it very difficult to analyze one measurement relative to another with any level of accuracy or repeatability.
Another shortcoming of conventional architecture 100 is that it is generally asynchronous. Again, this is because architecture 100 is built around a collection of discrete instruments 104, 106, and 108. Although the instruments 104, 106, and 108 are connected to the triggering buss 116 and can therefore be made to respond to the same triggering events, the instruments 104, 106, and 108 do not typically operate in conjunction with the same clock reference. This makes it very difficult to predict when the instruments will actually respond to the triggering events. Consequently, it may be difficult to achieve good correlation between measurements made by different instruments.
Still another shortcoming of having an architecture based upon a collection of discrete instruments 104, 106, and 108 is that there is frequently a duplication of functions, thereby increasing costs and space requirements. For example, each of the different instruments 104, 106, and 108 typically has its own input section providing signal conditioning, circuit protection, and ranging functions. However, this duplication of functions often becomes apparent especially when using the instruments 104, 106, and 108 to make measurements at a single node of the UUT.
Yet another shortcoming is that custom cabling is usually required between the test equipment 100 and a UUT. Significant costs are generally associated with any custom hardware. Further, the switch matrix 110 is typically implemented with relays, which are not only costly but also frequently unreliable.
It would therefore be desirable to have test instrument architecture that can closely simulate final operating environments of analog and mixed-signal electronic circuit assemblies and accurately evaluate their performance in these simulated environments. Such test instrument architecture would be useful for performing functional testing of the circuit assemblies during their manufacture. It would also be highly desirable to have an analog test instrument that provides better correlation between multiple test measurements.
With the foregoing background in mind, it is an object of the invention to provide a test instrument that can perform testing of analog and mixed-signal electronic circuit assemblies with higher degrees of accuracy and repeatability.
Another object of the invention is to provide an analog test instrument that can achieve better correlation between test measurements.
Still another object of the invention is to provide an analog test instrument that is less costly and more reliable.
The foregoing and other objects are achieved in an analog test instrument having a plurality of channels, each channel being coupled to a node of a unit under test, and each channel including a plurality of driver and measurement circuits. In a preferred embodiment, each channel includes driver circuitry coupled to an output buffer for driving test stimuli at a node of the unit under test, and each channel includes a plurality of measurement circuits coupled to a shared input buffer for measuring parameters of signals provided at the node of the unit under test.
According to one feature, each channel further includes triggering circuitry coupled to the driver and measurement circuits for providing shared timing events to the driver and measurement circuits and the plurality of channels.
In another embodiment, the analog test instrument includes a master clock reference coupled to each channel for synchronizing the inputs, outputs, and internal operation of the channels.
In another embodiment, test stimuli are applied to a portion of the nodes of an analog circuit and responses, generated by the analog circuit, are measured on another portion of the nodes. Further, the responses are sampled by a digitizer in each of the channels. The sampled responses are then stored in a memory included in the analog test instrument. When one of the response measurements indicates that a test has failed, the stored samples are analyzed for determining a cause of the failure.
In another embodiment, trigger events are periodically applied to driver and measurement circuits in each channel by the triggering circuitry in one of the channels. Test stimuli are then automatically applied and responses are automatically observed at nodes of an analog circuit under test. The test stimuli are applied and the responses are observed at times corresponding to the periodic trigger events. Next, the observed responses are evaluated, thereby determining whether the analog circuit under test is functioning properly.
Still further objects and advantages will become apparent from a consideration of the ensuing description and drawings.